HD6433802H Datasheet, PDF (179/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

8.9 Port A
8.9.1 Overview
Port A is a 4-bit I/O port, configured as shown in figure 8.8.
Port A
PA₃/COM₄
PA₂/COM₃
PA₁/COM₂
PA₀/COM₁
Figure 8.8 Port A Pin Configuration
8.9.2 Register Configuration and Description
Table 8.23 shows the port A register configuration.
Table 8.23 Port A Registers
Name
Port data register A
Port control register A
Abbrev.
PDRA
PCRA
R/W
Initial Value Address
R/W
H'F0
H'FFDD
W
H'F0
H'FFED
1. Port data register A (PDRA)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
PA ₃
PA ₂
PA ₁
PA ₀
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
PDRA is an 8-bit register that stores data for port A pins PA₃ to PA₀. If port A is read while
PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If
port A is read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
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