HD6433802H Datasheet, PDF (383/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

SSR—Serial status register
H'AC
SCI3
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
OER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPBR
0
R
0
MPBT
0
R/W
Multiprocessor bit transfer
0 A 0 multiprocessor bit is transmitted
1 A 1 multiprocessor bit is transmitted
Multiprocessor bit receive
0 Data in which the multiprocessor bit is 0 has been received
1 Data in which the multiprocessor bit is 1 has been received
Transmit end
0 Transmission in progress
[Clearing conditions] • After reading TDRE = 1, cleared by writing 0 to TDRE
• When data is written to TDR by an instruction
1 Transmission ended
[Setting conditions] • When bit TE in serial control register3 (SCR3) is cleared to 0
• When bit TDRE is set to 1 when the last bit of a transmit character is sent
Parity error
0 Reception in progress or completed normally
[Clearing conditions] After reading PER = 1, cleared by writing 0 to PER
1 A parity error has occurred during reception
[Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM) in the serial mode register (SMR)
Framing error
0 Reception in progress or completed normally
[Clearing conditions] After reading FER = 1, cleared by writing 0 to FER
1 A framing error has occurred during reception
[Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun error
0 Reception in progress or completed
[Clearing conditions] After reading OER = 1, cleared by writing 0 to OER
1 An overrun error has occurred during reception
[Setting conditions] When the next serial reception is completed with RDRF set to 1
Receive data register full
0 There is no receive data in RDR
[Clearing conditions] • After reading RDRF = 1, cleared by writing 0 to RDRF
• When RDR data is read by an instruction
1 There is receive data in RDR
[Setting conditions] When reception ends normally and receive data is transferred from RSR to RDR
Transmit data register empty
0 Transmit data written in TDR has not been transferred to TSR
[Clearing conditions] • After reading TDRE = 1, cleared by writing 0 to TDRE
• When data is written to TDR by an instruction
1 Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR
[Setting conditions] • When bit TE in serial control register3 (SCR3) is cleared to 0
• When data is transferred from TDR to TSR
Note: * Only a write of 0 for flag clearing is possible.
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