HD6433802H Datasheet, PDF (252/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

10.2.8 Bit rate register (BRR)
Bit
Initial value
Read/Write
7
BRR7
1
R/W
6
BRR6
1
R/W
5
BRR5
1
R/W
4
BRR4
1
R/W
3
BRR3
1
R/W
2
BRR2
1
R/W
1
BRR1
1
R/W
0
BRR0
1
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
32.8 kHz
38.4 kHz
B Bit Rate
Error
Error
(bit/s) n N (%) n N (%) n
110
Cannot be used, — — — —
150
as error
030 2
200
exceeds 3% 0 2 0 0
250
——— 0
300
010 0
600
000 0
1200
——— 0
2400
——— 0
4800
——— —
9600
——— —
19200
——— —
31250
——— 0
38400
——— —
OSC
2 MHz
2.4576 MHz
Error
Error
N (%) n N (%) n
— — 2 21 –0.83 —
12 0.16 3 3 0 2
155 0.16 3 2 0 —
124 0 0 153 –0.26 0
103 0.16 3 1 0 2
51 0.16 3 0 0 0
25 0.16 2 1 0 0
12 0.16 2 0 0 0
—— 0 7 0 0
—— 0 3 0 —
—— 0 1 0 —
0 0 ——— 0
—— 0 0 0 —
4 MHz
Error
N (%)
——
25 0.16
——
249 0
12 0.16
103 0.16
51 0.16
25 0.16
12 0.16
——
——
10
——
234