HD6433802H Datasheet, PDF (222/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 1: Event counter PWM enable
Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC.
Bit 1
ECPWME
0
1
Description
AEC PWM halted, IRQAEC selected
AEC PWM operation enabled, IRQAEC deselected
(initial value)
Bit 0: Reserved bit
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
6. Event counter control register (ECCR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 —
0
0
0
0
0
0
0
0
R/W
R/W R/W R/W R/W R/W
R/W R/W
ECCR performs counter input clock and IRQAEC/IECPWM control.
Bits 7 and 6: AEC clock select H (ACKH1, ACKH0)
Bits 7 and 6 select the clock used by ECH.
Bit 7
ACKH1
0
1
Bit 6
ACKH0
0
1
0
1
Description
AEVH pin input
ø/2
ø/4
ø/8
(initial value)
204