HD6433802H Datasheet, PDF (89/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

2. Interrupts IRQ₁ and IRQ₀
Interrupts IRQ₁ and IRQ₀ are requested by input signals to pins IRQ₁ and IRQ₀. These interrupts
are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits
IEG1 and IEG0 in IEGR.
When these pins are designated as pins IRQ₁ and IRQ₀ in port mode register B and 2 and the
designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt.
Recognition of these interrupt requests can be disabled individually by clearing bits IEN1 and
IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ₁ and IRQ₀ interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
numbers 5 and 4 are assigned to interrupts IRQ₁ and IRQ₀. The order of priority is from IRQ₀
(high) to IRQ₁ (low). Table 3.2 gives details.
3. IRQAEC Interrupt
The IRQAEC interrupt is requested by an input signal to pin IRQAEC. This interrupt is detected
by rising edge, falling edge, or both edge sensing, depending on the settings of bits AIAGS1 and
AIAGS0 in AEGSR.
When bit IENEC2 in IENR1 is 1 and the designated edge is input, the corresponding bit in IRR1 is
set to 1, requesting an interrupt.
When IRQAEC interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 6 is assigned to the IRQAEC interrupt. Table 3.2 gives details.
3.3.4 Internal Interrupts
There are 7 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 18,
15, 14, 12, and 11 are assigned to these interrupts. Table 3.2 shows the order of priority of
interrupts from on-chip peripheral modules.
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