HD6433802H Datasheet, PDF (126/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

5.5 Subsleep Mode
5.5.1 Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter, and PWM is halted. As long as a minimum required voltage is applied, the contents of
CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules are
retained. I/O ports keep the same states as before the transition.
5.5.2 Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer F, asynchronous counter, SCI3,
IRQAEC, IRQ₁, IRQ₀, WKP₇ to WKP₀) or by a low input at the RES pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
Interrupt signal and system clock are mutually asynchronous. Synchronization error time in a
maximum is 2/ø_SUB (s).
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in 5.3.2, Clearing
Standby Mode.
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