HD6433802H Datasheet, PDF (226/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 1: Counter reset control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
0
1
Description
ECH is reset
ECH reset is cleared and count-up function is enabled
(initial value)
Bit 0: Counter reset control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL
0
1
Description
ECL is reset
ECL reset is cleared and count-up function is enabled
(initial value)
8. Event counter H (ECH)
Bit
Initial Value
Read/Write
7
ECH7
0
R
6
ECH6
0
R
5
ECH5
0
R
4
ECH4
0
R
3
ECH3
0
R
2
ECH2
0
R
1
ECH1
0
R
0
ECH0
0
R
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Either the external asynchronous event AEVH pin or the overflow signal from lower 8-bit counter
ECL can be selected as the input clock source. ECH can be cleared to H'00 by software, and is
also initialized to H'00 upon reset.
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