HD6433802H Datasheet, PDF (196/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

9.2.5 Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
9.3 Timer F
9.3.1 Overview
Timer F is a 16-bit timer with a built-in output compare function. Timer F also provides for
counter resetting, interrupt request generation, toggle output, etc., using compare match signals.
Timer F can also be used as two independent 8-bit timers (timer FH and timer FL).
1. Features
Features of timer F are given below.
• Choice of four internal clock sources (ø/32, ø/16, ø/4, øw/4)
• TMOFH pin toggle output provided using a single compare match signal (toggle output initial
value can be set)
• Counter resetting by a compare match signal
• Two interrupt sources: one compare match, one overflow
• Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode).
Timer FH 8-Bit Timer*
Timer FL
8-Bit Timer/Event Counter
Internal clock
Choice of 4 (ø/32, ø/16, ø/4, øw/4)
Toggle output
One compare match signal, output to One compare match signal, output to
TMOFH pin(initial value settable)
TMOFL pin (initial value settable)
Counter reset
Counter can be reset by compare match signal
Interrupt sources One compare match
One overflow
Note: * When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal.
• Operation in watch mode, subactive mode, and subsleep mode
When øw/4 is selected as the internal clock, timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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