HD6433802H Datasheet, PDF (387/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

TCSRF—Timer control/status register F
H'B7
Timer F
Bit
Initial value
Read/Write
7
OVFH
0
R/(W)^*
6
CMFH
0
R/(W)^*
5
OVIEH
0
R/W
4
CCLRH
0
R/W
3
OVFL
0
R/(W)^*
2
CMFL
0
R/W ^*
1
OVIEL
0
R/W
0
CCLRL
0
R/W
Counter clear L
0 TCFL clearing by compare match is disabled
1 TCFL clearing by compare match is enabled
Timer overflow interrupt enable L
0 TCFL overflow interrupt request is disabled
1 TCFL overflow interrupt request is enabled
Compare match flag L
0 Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
1 Setting conditions:
Set when the TCFL value matches the OCRFL value
Timer overflow flag L
0 Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting conditions:
Set when TCFL overflows from H'FF to H'00
Counter clear H
0 16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1 16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Timer overflow interrupt enable H
0 TCFH overflow interrupt request is disabled
1 TCFH overflow interrupt request is enabled
Compare match flag H
0 Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
1 Setting conditions:
Set when the TCFH value matches the OCRFH value
Timer overflow flag H
0 Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1 Setting conditions:
Set when TCFH overflows from H'FF to H'00
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
369