MC9S12NE64_06 Datasheet, PDF (77/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Definition
Table 2-8. FCNFG Field Descriptions (continued)
Field
6
CCIE
5
KEYACC
Description
Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the Flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see Section 2.3.2.7, “Flash Status Register (FSTAT)”)
is set.
Enable Security Key Writing
0 Flash writes are interpreted as the start of a command write sequence.
1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid
data.
2.3.2.5 Flash Protection Register (FPROT)
The FPROT register defines which Flash sectors are protected against program or erase operations.
All bits in the FPROT register are readable and writable with restrictions except for RNV[6] which is only
readable (see Section 2.3.2.6, “Flash Protection Restrictions”).
During reset, the FPROT register is loaded from the Flash Configuration Field at address 0xFF0D. To
change the Flash protection that will be loaded during the reset sequence, the upper sector of the Flash
memory must be unprotected, then the Flash Protect/Security byte located as described in Table 2-1 must
be reprogrammed.
Trying to alter data in any of the protected areas in the Flash block will result in a protection violation error
and the PVIOL flag will be set in the FSTAT register. A mass erase of the Flash block is not possible if
any of the contained Flash sectors are protected.
Table 2-9. FPROT Field Descriptions
Field
Description
7
FPOPEN
Protection Function Bit — The FPOPEN bit determines the protection function for program or erase as shown
in Table 2-10.
0 FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS[1:0]
and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the main part
of the Flash block to be protected while a small address range can remain unprotected for EEPROM
emulation.
1 FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS[1:0]
and FPLS[1:0] bits.
6
Reserved Nonvolatile Bit — The RNV[6] bit must remain in the erased state 1 for future enhancements.
RNV[6]
5
FPHDIS
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in the higher address space of the Flash block.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4:3
Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected
FPHS[1:0] area as shown in Table 2-11. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
77