MC9S12NE64_06 Datasheet, PDF (384/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 13 Penta Output Voltage Regulator (VREGPHYV1)
13.4.3 POR - Power-On Reset
This functional block monitors output VDD. If V_DD is below V_PORD, signal POR is high, if it
exceeds V_PORD, the signal goes low. The transition to low forces the CPU in the power-on
sequence.
Due to its role during chip power-up this module must be active in all operating modes of
VREG_PHY.
13.4.4 LVR - Low Voltage Reset
Block LVR monitors the primary output voltage V_DD. If it drops below the assertion level (V_LVRA)
signal LVR asserts and when rising above the deassertion level (V_LVRD) signal LVR negates again.
The LVR function is available only in Full Performance Mode.
13.4.5 CTRL - Regulator Control
This part contains the register block of VREG_PHY and further digital functionality needed to
control the operating modes. CTRL also represents the interface to the digital core logic.
13.5 Resets
13.5.1 General
This section describes how VREG_PHY controls the reset of the MCU.The reset values of
registers and signals are provided in Section 13.3, “Memory Map and Registers.” Possible reset
sources are listed in Table 13-2.
Table 13-2. VREG_PHY - Reset Sources
Reset Source
Power-on Reset
Low Voltage Reset
Local Enable
always active
available only in Full
Performance Mode
13.5.2 Description of Reset Operation
13.5.2.1 Power-On Reset
During chip power-up the digital core may not work if its supply voltage V_DD is below the POR
deassertion level (V_PORD). Therefore signal POR which forces the other blocks of the device into
reset is kept high until V_DD exceeds V_PORD. Then POR becomes low and the reset generator of
the device continues the start-up sequence. The power-on reset is active in all operation modes of
VREG_PHY.
MC9S12NE64 Data Sheet, Rev. 1.1
384
Freescale Semiconductor