MC9S12NE64_06 Datasheet, PDF (379/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 13
Penta Output Voltage Regulator (VREGPHYV1)
13.1 Introduction
13.1.1 Overview
Block VREG_PHY is a penta output voltage regulator providing five separate 2.5V (typ) supplies
differing in the amount of current that can be sourced. The regulator input voltage is 3.3V+/-10% .
13.1.2 Features
The block VREG_PHY includes these distinctive features:
• Five parallel, linear voltage regulators
— Bandgap reference
• Power On Reset (POR)
• Low Voltage Reset (LVR)
13.1.3 Modes of Operation
There are three modes VREG_PHY can operate in:
• Full Performance Mode (FPM) (CPU is not in Stop Mode)
The regulator is active, providing the nominal supply voltage of 2.5V with full current
sourcing capability at all outputs. Features LVR (Low Voltage Reset) and POR (Power-On
Reset) are available.
• Reduced Power Mode (RPM) (CPU is in Stop Mode)
The purpose is to reduce power consumption of the device. The output voltage may degrade
to a lower value than in Full Performance Mode, additionally the current sourcing
capability is substantially reduced. Only the POR is available in this mode, LVR are
disabled.
• Shutdown Mode
Controlled by VREGEN (see device level specification for connectivity of VREGEN).
This mode is characterized by minimum power consumption. The regulator outputs are in
a high impedance state, only the POR feature is available, LVR is disabled.
This mode must be used to disable the chip internal regulator VREG_PHY, i.e. to bypass
the VREG_PHY to use external supplies.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
379