MC9S12NE64_06 Datasheet, PDF (59/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Clock Description
1.3 System Clock Description
The clock and reset generator provides the internal clock signals for the core and all peripheral modules.
Figure 1-5 shows the clock connections from the CRG to all modules. See the CRG block description
chapter for details on clock generation.
core clock
S12_CORE
EXTAL
CRG
XTAL
bus clock
oscillator clock
FLASH
RAM
TIM
ATD
PIM
SCI
SPI
IIC
EMAC
Figure 1-5. Clock Connections
EPHY
VREG_PHY
1.4 Modes of Operation
There are eight possible modes of operation available on the MC9S12NE64. Each mode has an associated
default memory map and external bus configuration.
1.4.1 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and
provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are
latched into these bits on the rising edge of the RESET signal. The ROMCTL signal allows the setting of
the ROMON bit in the MISC register thus controlling whether the internal FLASH is visible in the memory
map. ROMON = 1 means the FLASH is visible in the memory map. The state of the ROMCTL pin is
latched into the ROMON bit in the MISC register on the rising edge of the RESET signal.
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
59