MC9S12NE64_06 Datasheet, PDF (413/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Definition
Field
7
RDRK
4
RDPE
1
RDPB
0
RDPA
Table 15-10. RDRIV Field Descriptions
Description
Reduced Drive of Port K
0 All port K output pins have full drive enabled.
1 All port K output pins have reduced drive enabled.
Reduced Drive of Port E
0 All port E output pins have full drive enabled.
1 All port E output pins have reduced drive enabled.
Reduced Drive of Port B
0 All port B output pins have full drive enabled.
1 All port B output pins have reduced drive enabled.
Reduced Drive of Ports A
0 All port A output pins have full drive enabled.
1 All port A output pins have reduced drive enabled.
15.3.2.12 External Bus Interface Control Register (EBICTL)
R
W
Reset:
Peripheral
All other modes
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-16. External Bus Interface Control Register (EBICTL)
0
ESTR
0
1
Read: Anytime (provided this register is in the map)
Write: Refer to individual bit descriptions below
The EBICTL register is used to control miscellaneous functions (i.e., stretching of external E clock).
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
Table 15-11. EBICTL Field Descriptions
Field
0
ESTR
Description
E Clock Stretches — This control bit determines whether the E clock behaves as a simple free-running clock or
as a bus control signal that is active only for external bus cycles.
Normal and Emulation: write once
Special: write anytime
0 E never stretches (always free running).
1 E stretches high during stretched external accesses and remains low during non-visible internal accesses.
This bit has no effect in single-chip modes.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
413