MC9S12NE64_06 Datasheet, PDF (355/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Descriptions
RESET — EPHY Reset
Resetting a port is accomplished by setting this bit to 1.
1 = The PHY will reset the port’s status and registers to the default values. The PHY will also reset
the PHY to its initial state. After the reset is complete, the PHY clears this bit automatically.
The reset process will be completed within 1.3 ms of this bit being set. While the preamble is
suppressed, the management interface must not receive an ST within three MDC clock cycles
following a software reset.
0 = No effect
LOOPBACK — Digital Loopback Mode
Determines Digital Loopback Mode
1 = Enables digital loopback mode. Port will be placed in loopback mode. Loopback mode will
allow the TXD data to be sent to the RXD data circuitry within 512 bit times. The PHY will be
isolated from the medium (no transmit or receive to the medium allowed) and the MII_COL
signal will remain de-asserted, unless this bit is set.
0 = Disables digital loopback mode
DATARATE — Speed Selection
The link speed will be selected either through the auto-negotiation process or by manual speed
selection. ANE allows manual speed selection while it is set to 0. While auto-negotiation is enabled,
DATARATE can be read or written but its value is not required to reflect speed of the link.
1 = While auto-negotiation is disabled, selects 100 Mbps operation
0 = While auto-negotiation is disabled, selects 10 Mbps operation
ANE — Auto-Negotiation Enable
The ANE bit determines whether the A/N process is enabled. When auto-negotiation is disabled,
DATARATE and DPLX determine the link configuration. While auto-negotiation is enabled, bits
DATARATE and DPLX do not affect the link.
1 = Enables auto-negotiation
0 = Disables auto-negotiation
PDWN — Power Down
When this bit is set, the port is placed in a low power consumption mode.
1 = Port is placed in a low power consumption mode. Normal operation will be allowed within 0.5 s
after PDWN and ISOL are changed to 0. During a transition to power-down mode (or if already
in power down mode), the port will respond only to management function requests through the
MI interface. All other port operations will be disabled. When power-down mode is exited, all
register values are maintained. The port will start its operation based on the register values.
0 = Normal operation
ISOL — Isolate
1 = Isolates the port’s data path signals from the MII. The port will not respond to changes on
MII_TXDx, MII_TXEN, and MII_TXER inputs, and it will present high impedance on
MII_TXCLK, MII_RXCLK, MII_RXDV, MII_RXER, MII_RXDx, MII_COL, and MII_CRS
outputs. The port will respond to management transactions while in isolate mode.
0 = Normal operation
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
355