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MC9S12NE64_06 Datasheet, PDF (519/554 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Reset, Oscillator, and PLL Electrical Characteristics
Cp
VDDPLL
Cs
R
Phase
XFC Pin
VCO
fosc
1
fref
refdv+1
â
KΦ
KV
fvco
Detector
fcmp
Loop Divider
1
1
synr+1
2
Figure 18-22. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K1, f1 and ich from Table A-13.
The grey boxes show the calculation for fVCO = 50 MHz and fref = 1 MHz. E.g., these frequencies are used
for fOSC = 4 MHz and a 25 MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
KV = K1 â
e-(--fK--1--1--â--â
--f-1-v--c-V--o-=--) â100 â
e(---6---â0---1-â--0---50---0---=-) -90.48MHz/V
The phase detector relationship is given by:
KΦ = â ich â
KV
= 316.7Hz/â¦
ich is the current in tracking mode.
The loop bandwidth fC should be chosen to fulï¬ll the Gardnerâs stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
fC < ----------2-----â
---ζ----â
---f--r--e---f----------
Ï
â
â
â
ζ
+
1 + ζ2â â
--1---
10
â
fC
<
4---f--râ
--e-1--f-0- ;(ζ
=
0.9 )
fC < 25kHz
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
519
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