MC9S12NE64_06 Datasheet, PDF (57/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Signal Description
1.2.3.60 PHY_RBIAS — EPHY Bias Control Resistor
Connect a 1.0% external resistor, RBIAS, between PHY_RBIAS pin and PHY_VSSA. This resistor must
be placed as near as possible to the chip pin. Stray capacitance must be kept to less than 10 pF (> 50 pF
may cause instability). No high-speed signals are allowed in the region of RBIAS.
1.2.4 Power Supply Pins
1.2.4.1 V_DDX1, V_DDX2, V_SSX1, V_SSX2 — Power & Ground Pins for I/O & Internal
Voltage Regulator
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded.
1.2.4.2 V_DDR/V_REGEN — Power Pin for Internal Voltage Regulator
External power for internal voltage regulator.
1.2.4.3 V_DD1, V_DD2, V_SS1, V_SS2 — Core Power Pins
Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal
voltage regulator. No static load is allowed on these pins. The internal voltage regulator is turned off, if
VDDR/VREGEN is tied to ground.
1.2.4.4 V_DDA, V_SSA — Power Supply Pins for ATD and VREG_PHY
VDDA and VSSA are the power supply and ground input pins for the voltage regulator and the
analog-to-digital converter.
1.2.4.5 PHY_VDDA, PHY_VSSA — Power Supply Pins for EPHY Analog
Power is supplied to the Ethernet physical transceiver (EPHY) PLLs through PHY_VDDA and
PHY_VSSA. This 2.5V supply is derived from the internal voltage regulator. No static load is allowed on
these pins. The internal voltage regulator is turned off, if VDDR/VREGEN is tied to ground.
1.2.4.6 PHY_VDDRX, PHY_VSSRX — Power Supply Pins for EPHY Receiver
Power is supplied to the Ethernet physical transceiver (EPHY) receiver through PHY_VDDRX and
PHY_VSSRX. This 2.5V supply is derived from the internal voltage regulator. No static load is allowed
on these pins. The internal voltage regulator is turned off, if VDDR/VREGEN is tied to ground.
1.2.4.7 PHY_VDDTX, PHY_VSSTX — Power Supply Pins for EPHY Transmitter
External power is supplied to the Ethernet physical transceiver (EPHY) transmitter through PHY_VDDTX
and PHY_VSSTX. This 2.5 V supply is derived from the internal voltage regulator. No static load is
allowed on these pins. The internal voltage regulator is turned off, if V_DDR/V_REGEN is tied to ground.
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
57