MC9S12NE64_06 Datasheet, PDF (194/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Timer Module (TIM16B4CV1)
6.3.2.10 Timer Interrupt Enable Register (TIE)
7
6
5
4
3
2
1
0
R
0
0
0
0
C7I
C6I
C5I
C4I
W
Reset
0
0
0
0
0
0
0
0
Figure 6-16. Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Table 6-12. TIE Field Descriptions
Field
7:4
C7I:C0I
Description
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
6.3.2.11 Timer System Control Register 2 (TSCR2)
7
6
5
4
3
2
1
0
R
0
0
0
TOI
TCRE
PR2
PR1
PR0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-17. Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
Table 6-13. TSCR2 Field Descriptions
Field
7
TOI
3
TCRE
2
PR[2:0]
Description
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF
will never be set when TCNT is reset from 0xFFFF to 0x0000.
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 6-14.
MC9S12NE64 Data Sheet, Rev. 1.1
194
Freescale Semiconductor