MC9S12NE64_06 Datasheet, PDF (474/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Debug Module (DBGV1)
18.3 Memory Map and Register Definition
A summary of the registers associated with the DBG sub-block is shown in Figure 18-3. Detailed
descriptions of the registers and bits are given in the subsections that follow.
18.3.1 Module Memory Map
Table 18-2. DBGV1 Memory Map
Address
Offset
4
5
6
8
9
A
B
E
F
Use
Debug Control Register (DBGC1)
Debug Status and Control Register (DBGSC)
Debug Trace Buffer Register High (DBGTBH)
Debug Trace Buffer Register Low (DBGTBL)
Debug Count Register (DBGCNT)
Debug Comparator C Extended Register (DBGCCX)
Debug Comparator C Register High (DBGCCH)
Debug Comparator C Register Low (DBGCCL)
Debug Control Register 2 (DBGC2) / (BKPCT0)
Debug Control Register 3 (DBGC3) / (BKPCT1)
Debug Comparator A Extended Register (DBGCAX) / (/BKP0X)
Debug Comparator A Register High (DBGCAH) / (BKP0H)
Debug Comparator A Register Low (DBGCAL) / (BKP0L)
Debug Comparator B Extended Register (DBGCBX) / (BKP1X)
Debug Comparator B Register High (DBGCBH) / (BKP1H)
Debug Comparator B Register Low (DBGCBL) / (BKP1L)
Access
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
18.3.2 Register Descriptions
This section consists of the DBG register descriptions in address order. Most of the register bits can be
written to in either BKP or DBG mode, although they may not have any effect in one of the modes.
However, the only bits in the DBG module that can be written while the debugger is armed (ARM = 1) are
DBGEN and ARM
Name¹
DBGC1
Bit 7
6
5
4
3
2
R
0
DBGEN
ARM TRGSEL BEGIN DBGBRK
W
1
Bit 0
CAPMOD
R AF
BF
CF
0
DBGSC
W
TRG
= Unimplemented or Reserved
Figure 18-3. DBG Register Summary
MC9S12NE64 Data Sheet, Rev. 1.1
474
Freescale Semiconductor