MC9S12NE64_06 Datasheet, PDF (124/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9NE64V1)
This register always reads back the status of the associated pins. This can be also used to detect overload
or short circuit conditions on output pins.
3.3.2.4.3 Data Direction Register (DDRH)
Module Base + $1A
Read:
Write:
Reset:
Bit 7
0
—
6
DDRH6
0
5
DDRH5
0
4
DDRH4
0
3
DDRH3
0
2
DDRH2
0
1
DDRH1
0
Bit 0
DDRH0
0
= Reserved or unimplemented
Figure 3-25. Port H Data Direction Register (DDRH)
Read:Anytime.
Write:Anytime.
This register configures each port H pin as either input or output.
DDRH[6:0] — Data Direction Port H
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTH
or PTIH registers, when changing the DDRH register.
If the EMAC MII external interface is enabled, pins PH[6:0] become MII_TXER, MII_TXEN,
MII_TXCLK, MII_TXD[3:0]. In that case, DDRH[6:0] bits have no effect on their I/O direction.
3.3.2.4.4 Reduced Drive Register (RDRH)
Module Base + $1B
Read:
Write:
Reset:
Bit 7
0
—
6
RDRH6
0
5
RDRH5
0
4
RDRH4
0
3
RDRH3
0
2
RDRH2
0
1
RDRH1
0
Bit 0
RDRH0
0
= Reserved or unimplemented
Figure 3-26. Port H Reduced Drive Register (RDRH)
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port H output pin as either full or reduced. If the port is
used as input this bit is ignored.
RDRH[6:0] — Reduced Drive Port H
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
MC9S12NE64 Data Sheet, Rev. 1.1
124
Freescale Semiconductor