MC9S12NE64_06 Datasheet, PDF (315/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Descriptions
RXACT — Receiver Active Status
This is a read-only status bit that indicates activity in the EMAC receiver. RXACT is asserted when
MII_RXDV is asserted and clears when the EMAC has finished processing the receive frame after
MII_RXDV is negated.
1 = Receiver is active.
0 = Receiver is idle.
RFCE — Reception Flow Control Enable
This bit can be written anytime, but the user must not change this bit while EMACE is set.
While this bit is set, the receiver detects PAUSE frames (full-duplex mode only). Upon PAUSE frame
detection, the transmitter stops transmitting data frames for a given duration (PAUSE time in received
frame). The value of the PAUSE timer counter is updated when a valid PAUSE control frame is
received.
While this bit is clear, the receiver ignores any PAUSE frames.
1 = Upon PAUSE frame detection, transmitter stops for a given duration.
0 = Received PAUSE control frames are ignored.
PROM — Promiscuous Mode
This bit can be written anytime, but the user must not change this bit while EMACE is set. Changing
values while the receiver is active may affect the outcome of the receive filters.
While set, the address recognition filter is ignored and all frames are received regardless of destination
address.
While clear, the destination address is checked for incoming frames.
1 = All frames are received regardless of address.
0 = Destination address is checked for incoming frames.
CONMC — Conditional Multicast
This bit can be written anytime, but the user must not change this bit while EMACE is set. Changing
values while the receiver is active may affect the outcome of the receive filters.
While set, the multicast hash table is used to check all multicast addresses received unless the PROM
bit is set.
While clear, all multicast address frames are accepted.
1 = Multicast hash table is used for checking multicast addresses.
0 = Multicast address frames are accepted.
BCREJ — Broadcast Reject
This bit can be written anytime, but the user must not change this bit while EMACE is set.
While set, all broadcast addresses are rejected unless the PROM bit is set.
While clear, all broadcast address frames are accepted.
1 = All broadcast address frames are rejected.
0 = All broadcast address frames are accepted.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
315