MC9S12NE64_06 Datasheet, PDF (134/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.6.7 Wired-Or Mode Register (WOML)
Address Offset: $__2E
Read:
Write:
Reset:
Bit 7
0
—
6
WOML6
0
5
WOML5
0
4
WOML4
0
3
WOML3
0
2
WOML2
0
1
WOML1
0
Bit 0
WOML0
0
= Reserved or unimplemented
Figure 3-45. Port L Wired-Or Mode Register (WOML)
Read:Anytime.
Write:Anytime.
This register configures the output pins as wired-or. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. This bit has no effect on pins used as inputs.
WOML[6:0] — Wired-Or Mode Port L
1 = Open-drain mode enabled for output buffers.
0 = Open-drain mode disabled for output buffers.
3.4 Functional Description
Each pin can act as general-purpose I/O. In addition the pin can act as an output from a peripheral module
or an input to a peripheral module.
A set of configuration registers is common to all ports. All registers can be written at any time, however a
specific configuration might not become active.
Example:
Selecting a pull-up resistor. This resistor does not become active while the port is used as a push-pull
output.
3.4.1 I/O Register
This register holds the value driven out to the pin if the port is used as a general-purpose I/O.
Writing to this register has only an effect on the pin if the port is used as general-purpose output. When
reading this address, the value of the pins are returned if the data direction register bits are set to 0.
If the data direction register bits are set to 1, the contents of the I/O register is returned. This is independent
of any other configuration (Figure 3-46).
3.4.2 Input Register
This is a read-only register and always returns the value of the pin (Figure 3-46).
Data direction register
MC9S12NE64 Data Sheet, Rev. 1.1
134
Freescale Semiconductor