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MC9S12NE64_06 Datasheet, PDF (191/554 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Memory Map and Register Deï¬nition
Table 6-6. TSCR1 Field Descriptions (continued)
Field
5
TSFRZ
4
TFFCA
Description
Timer Stops While in Freeze Mode
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
TSFRZ does not stop the pulse accumulator.
Timer Fast Flag Clear All
0 Allows the timer ï¬ag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010â0x001F)
causes the corresponding channel ï¬ag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF ï¬ag. Any access to the PACNT registers (0x0022, 0x0023) clears
the PAOVF and PAIF ï¬ags in the PAFLG register (0x0021). This has the advantage of eliminating software
overhead in a separate clear sequence. Extra care is required to avoid accidental ï¬ag clearing due to
unintended accesses.
6.3.2.7 Timer Toggle On Overï¬ow Register 1 (TTOV)
7
6
5
4
3
2
1
0
R
0
0
0
0
TOV7
TOV6
TOV5
TOV4
W
Reset
0
0
0
0
0
0
0
0
Figure 6-13. Timer Toggle On Overï¬ow Register 1 (TTOV)
Read: Anytime
Write: Anytime
Table 6-7. TTOV Field Descriptions
Field
7:4
TOV[7:4]
Description
Toggle On Overï¬ow Bits â TOVx toggles output compare pin on overï¬ow. This feature only takes effect when
in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override
events.
0 Toggle output compare pin on overï¬ow feature disabled.
1 Toggle output compare pin on overï¬ow feature enabled.
6.3.2.8 Timer Control Register 1 (TCTL1)
7
R
OM7
W
6
OL7
5
OM6
4
OL6
3
OM5
2
OL5
1
OM4
0
OL4
Reset
0
0
0
0
0
0
0
0
Figure 6-14. Timer Control Register 1 (TCTL1)
Read: Anytime
Write: Anytime
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
191
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