MC9S12NE64_06 Datasheet, PDF (143/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Signal Description
Voltage
Regulator
Power-on Reset
Low Voltage Reset ¹
RESET
Clock
XCLKS ^Monitor
EXTAL Oscil-
lator
XTAL
CRG
CM fail
OSCCLK
Reset
Generator
Clock Quality
Checker
COP RTI
XFC
V_DDPLL
V_SSPLL
PLLCLK
PLL
Registers
Clock and Reset
Control
1 _{Refer to the device overview section for availability of the low-voltage reset feature.}
Figure 4-1. CRG Block Diagram
4.2 External Signal Description
This section lists and describes the signals that connect off chip.
System Reset
Bus Clock
Core Clock
Oscillator Clock
Real-Time Interrupt
PLL Lock Interrupt
Self-Clock Mode
Interrupt
4.2.1 V_DDPLL, V_SSPLL — PLL Operating Voltage, PLL Ground
These pins provides operating voltage (V_DDPLL) and ground (V_SSPLL) for the PLL circuitry. This allows
the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required V_DDPLL
and V_SSPLL must be connected properly.
4.2.2 XFC — PLL Loop Filter Pin
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter
to eliminate the VCO input ripple. The value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. Refer to the device overview chapter
for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be
tied to V_DDPLL.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
143