MC9S12NE64_06 Datasheet, PDF (120/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.3.2 Input Register (PTIG)
Module Base + $11
Read:
Write:
Reset:
Bit 7
PTIG7
—
6
PTIG6
5
PTIG5
4
PTIG4
—
—
—
= Reserved or unimplemented
3
PTIG3
—
2
PTIG2
—
Figure 3-16. Port G Input Register (PTIG)
1
PTIG1
—
Bit 0
PTIG0
—
Read:Anytime.
Write:Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This also can be used to detect overload
or short circuit conditions on output pins.
3.3.2.3.3 Data Direction Register (DDRG)
Module Base + $12
Read:
Write:
Reset:
Bit 7
DDRG7
0
6
DDRG6
0
5
DDRG5
0
4
DDRG4
0
3
DDRG3
0
2
DDRG2
0
1
DDRG1
0
Bit 0
DDRG0
0
Figure 3-17. Port G Data Direction Register (DDRG)
Read:Anytime.
Write:Anytime.
This register configures each port G pin as either input or output.
DDRG[7:0] — Data Direction Port G
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
If the EMAC MII external interface is enabled, the pins G[6:0] are forced to be inputs and DDRG has no
effect on the them. Please refer to the EMAC block description chapter for details.
The DDRG bits revert to controlling the I/O direction of a pin when the EMAC MII external interface is
disabled.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTG
or PTIG registers, when changing the DDRG register.
MC9S12NE64 Data Sheet, Rev. 1.1
120
Freescale Semiconductor