MC9S12NE64_06 Datasheet, PDF (131/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

3.3.2.6 Port L Registers
Memory Map and Register Descriptions
3.3.2.6.1 I/O Register (PTL)
Module Base + $28
Read:
Write:
PHY
Reset:
Bit 7
0
—
6
5
4
PTL6
PTL5
PTL4
COLLED
0
0
0
= Reserved or unimplemented
3
PTL3
DUPLED
0
2
PTL2
SPDLED
0
Figure 3-39. Port L I/O Register (PTL)
1
PTL1
LNKLED
0
Bit 0
PTL0
ACTLED
0
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The EPHY LED drive takes precedence over general-purpose I/O function if the EPHYCTL0 LEDEN bit
is enabled. With the LEDEN bit set, PTL[4:0] become COLLED, DUPLED, SPDLED, LNKLED, and
ACTLED. Refer to EPHY block description chapter for more detail.
3.3.2.6.2 Input Register (PTIL)
Module Base + $29
Read:
Write:
Reset:
Bit 7
0
—
6
PTIL6
—
5
PTIL5
—
4
PTIL4
—
3
PTIL3
—
2
PTIL2
—
1
PTIL1
—
Bit 0
PTIL0
—
= Reserved or unimplemented
Figure 3-40. Port L Input Register (PTIL)
Read:Anytime.
Write:Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This also can be used to detect overload
or short circuit conditions on output pins.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
131