MC9S12NE64_06 Datasheet, PDF (139/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port
T
S
G
H
J[7:6]
J[3:0]
L
A
B
E
K
BKGD pin
Table 3-5. Port Reset State Summary
Data
Direction
input
input
input
input
input
input
input
Pull Mode
hiz
pull-up
hiz
hiz
pull-up
hiz
pull-up
Reset States
Red. Drive
Wired-Or
Mode
disabled
n/a
disabled disabled
disabled
n/a
disabled
n/a
disabled
n/a
disabled
n/a
disabled disabled
Interrupt
n/a
n/a
disabled
disabled
disabled
disabled
n/a
Refer to the MEBI block description chapter for details.
Refer to the BDM block description chapter for details.
3.6 Interrupts
Port G, H, and J generate a separate edge sensitive interrupt if enabled.
3.6.1
Interrupt Sources
Table 3-6. Port Integration Module Interrupt Sources
Interrupt Source
Interrupt
Flag
Local Enable
Global (CCR)
Mask
Port G
PIFG[7:0]
PIEG[7:0]
I Bit
Port H
PIFH[6:0]
PIEH[6:0]
I Bit
Port J
PIFJ[7:6],[3:0] PIEJ[7:6],[3:0]
I Bit
Interrupts
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
3.6.2 Recovery from Stop
The PIM_9NE64 can generate wake-up interrupts from stop on port G, H, and J. For other sources of
external interrupts please refer to the respective block description chapter.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
139