MC9S12NE64_06 Datasheet, PDF (136/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9NE64V1)
3.4.7 Port S
This port is associated with the serial SCI and SPI modules.
Port S pins PS[7:0] can be used either for general-purpose I/O, or with the SCI0, SCI1, and SPI
subsystems.
During reset, port S pins are configured as inputs with pull-up.
3.4.8 Port G
This port is associated with the EMAC module.
Port G pins PG[7:0] can be used either for general-purpose I/O or with the EMAC subsystems. Further the
Keypad Wake-Up function is implemented on pins G[7:0].
During reset, port G pins are configured as high-impedance inputs.
3.4.8.1 Interrupts
Port G offers eight general-purpose I/O pins with edge triggered interrupt capability in wired-or fashion.
The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on
per pin basis. All eight bits/pins share the same interrupt vector. Interrupts can be used with the pins
configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in STOP
or WAIT mode.
A digital filter on each pin prevents pulses (Figure 3-48) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 3-47 and
Table 3-4).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
t_pign
t_pval
Figure 3-47. Interrupt Glitch Filter on Port G, H, and J (PPS=0)
MC9S12NE64 Data Sheet, Rev. 1.1
136
Freescale Semiconductor