MC9S12NE64_06 Datasheet, PDF (383/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

13.3 Memory Map and Registers
Memory Map and Registers
13.3.1 Overview
VREG_PHY does not contain any CPU accessible registers.
13.4 Functional Description
13.4.1 General
Block VREG_PHY is a voltage regulator as depicted in Figure 13-1. The regulator functional
elements are the regulator core (REG), a power-on reset module (POR) and a low voltage reset
module (LVR). There is also the regulator control block (CTRL) which represents the interface to
the digital core logic but also handles the operating modes of VREG_PHY.
13.4.2 REG - Regulator Core
VREG_PHY, respectively its regulator core has five parallel, independent regulation loops (REG1
to REG5) that differ only in the amount of current that can be sourced to the connected loads.
Therefore only REG1, providing the supply at VDD/VSS, is explained. The principle is also valid
for REG2 to REG5.
The regulator is a linear series regulator with a bandgap reference in its Full Performance Mode
and a voltage clamp in Reduced Power Mode. All load currents flow from input VDDR or
VDDRAUX1,2,3 to VSS or VSSPLL or VSSAUX1,2,3, the reference circuits are connected to
VDDA and VSSA.
13.4.2.1 Full Performance Mode
In Full Performance Mode a fraction of the output voltage (VDD) and the bandgap reference
voltage are fed to an operational amplifier. The amplified input voltage difference controls the gate
of an output driver which basically is a large NMOS transistor connected to the output.
13.4.2.2 Reduced Power Mode
In Reduced Power Mode the driver gate is connected to a buffered fraction of the input
voltage(VDDR). The operational amplifier and the bandgap are disabled to reduce power
consumption.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
383