MC9S12NE64_06 Datasheet, PDF (311/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Descriptions
11.2.11 MII_MDC — MII Management Data Clock
This output signal provides a timing reference to the PHY for data transfers on the MII_MDIO signal.
MII_MDC is aperiodic and has no maximum high or low times. The maximum clock frequency is
2.5 MHz, regardless of the nominal period of MII_TXCLK and MII_RXCLK.
11.2.12 MII_MDIO — MII Management Data Input/Output
This bidirectional signal transfers control/status information between the PHY and EMAC. Control
information is driven by the EMAC synchronously with respect to MII_MDC and is sampled
synchronously by the PHY. Status information is driven by the PHY synchronously with respect to
MII_MDC and is sampled synchronously by the EMAC.
11.3 Memory Map and Register Descriptions
This section provides a detailed description of all registers accessible in the EMAC.
11.3.1 Module Memory Map
Table 11-3 gives an overview of all registers in the EMAC memory map. The EMAC occupies 48 bytes in
the memory space. The register address results from the addition of base address and address offset. The
base address is determined at the MCU level and is given in the device user guide. The address offset is
defined at the module level and is provided in Table 11-3.
Table 11-3. EMAC Module Memory Map
Address
Offset
$__00
$__01
$__02
$__03
$__04
$__05
$__06
$__07
$__08
$__09
$__0A
$__0B
$__0C
$__0D
$__0E
$__0F
$__10
$__11
Use
Network Control (NETCTL)
Reserved
Receive Control and Status (RXCTS)
Transmit Control and Status (TXCTS)
Ethertype Control (ETCTL)
Programmable Ethertype (ETYPE)
PAUSE Timer Value and Counter (PTIME)
Interrupt Event (IEVENT)
Interrupt Mask (IMASK)
Software Reset (SWRST)
Reserved
MII Management PHY Address (MPADR)
MII Management Register Address (MRADR)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
311