MC9S12NE64_06 Datasheet, PDF (542/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
Table A-32. Expanded Bus Timing Characteristics (3.3 V Range)
Conditions are VDDX = 3.3 V 5%, Junction Temperature -40˚C to +125˚C, C_LOAD = 50 pF
Num C
Rating
Symbol
Min
Typ
1
P Frequency of operation (E-clock)
2
P Cycle time
3
D Pulse width, E low
4
D _{Pulse width, E high} ¹
f_o
t_cyc
PW_EL
PW_EH
0
62.5
30
30
5
D Address delay time
6
D Address valid time to E rise (PW_EL–t_AD)
t_AD
t_AV
16
7
D Muxed address hold time
8
D Address hold to data valid
9
D Data hold to address
10
D Read data setup time
11
D Read data hold time
12
D Write data delay time
13
D Write data hold time
14
D _{Write data setup time}¹ _{(PWEH–tDDW)}
t_MAH
2
t_AHDS
7
t_DHA
2
t_DSR
15
t_DHR
0
t_DDW
t_DHW
2
t_DSW
15
15
D _{Address access time}¹
t_ACCA
29
16
D _{E high access time}¹ _{(PWEH–tDSR)}
t_ACCE
15
17
D Read/write delay time
18
D Read/write valid time to E rise (PW_EL–t_RWD)
t_RWD
t_RWV
16
19
D Read/write hold time
20
D Low strobe delay time
21
D Low strobe valid time to E rise (PW_EL–t_LSD)
t_RWH
2
t_LSD
t_LSV
16
22
D Low strobe hold time
23
D NOACC strobe delay time
24
D NOACC valid time to E rise (PW_EL–t_LSD)
t_LSH
2
t_NOD
t_NOV
16
25
D NOACC hold time
26
D IPIPO[1:0] delay time
27
D IPIPO[1:0] valid time to E rise (PW_EL–t_P0D)
t_NOH
2
t_P0D
2
t_P0V
16
28
D _{IPIPO[1:0] delay time}¹
t_P1D
2
29
D IPIPO[1:0] valid time to E fall
t_P1V
11
1_{Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.}
Max
16.0
16
15
14
14
14
14
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MC9S12NE64 Data Sheet, Rev. 1.1
542
Freescale Semiconductor