MC9S12NE64_06 Datasheet, PDF (213/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Definition
7.3.2.2 ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence but will not start a new sequence.
7
6
5
4
R
0
0
0
ETRIGSEL
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
0
ETRIGCH2
0
1
Figure 7-4. ATD Control Register 1 (ATDCTL1)
1
ETRIGCH1
1
0
ETRIGCH0
1
Read: Anytime
Write: Anytime
Table 7-3. ATDCTL1 Field Descriptions
Field
Description
7
ETRIGSEL
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3–0 inputs. See the device overview chapter for availability and connectivity of
ETRIG3–0 inputs. If ETRIG3–0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, that means still one of the AD channels (selected by ETRIGCH2–0) is the source for external trigger.
The coding is summarized in Table 7-4.
2–0
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3–0 inputs
ETRIGCH[2:0] as source for the external trigger. The coding is summarized in Table 7-4.
Table 7-4. External Trigger Channel Select Coding
ETRIGSEL ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is
0
0
0
0
AN0
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
AN7
ETRIG0¹
ETRIG1¹
ETRIG2¹
ETRIG3¹
1
1
X
X
Reserved
1 _{Only if ETRIG3–0 input option is available (see device overview chapter), else ETRISEL is}
ignored, that means external trigger source is still on one of the AD channels selected by
ETRIGCH2–0
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
213