MC9S12NE64_06 Datasheet, PDF (541/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Bus Timing
A.18 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure 18-25 with the actual timing
values shown on table Table A-32. All major bus signals are included in the diagram. Although both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
1, 2
3
4
ECLK
PE4
Addr/Data
(read)
PA, PB
5
9
data
6
16
15
10
11
addr
data
7
8
Addr/Data
(write)
data
PA, PB
12
addr
14
13
data
17
18
19
R/W
PE2
20
21
22
LSTRB
PE3
23
24
25
NOACC
PE7
PIPO0
PIPO1, PE6,5
26
27
28
29
Figure 18-25. General External Bus Timing
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
541