MC9S12NE64_06 Datasheet, PDF (366/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
LNK — Link Status
This is a duplicate of LNKSTAT bit 2 of the status register (1.2).
1 = Link is down
0 = Link is up
DPMD — Duplex Mode
1 = Full-duplex
0 = Half-duplex
SPD — Speed
1 = 100 Mbps
0 = 10 Mbps
ANNC — Auto-Negotiation Complete
This is a duplicate of ANCOMP bit 5 of the status register (1.5)
1 = A-N complete
0 = A-N not complete
PRCVD — Page Received
1 = Three identical and consecutive link code words have been received
0 = Three identical and consecutive link code words have not been received
ANCMODE — Auto-Negotiation (A-N) Common Operating Mode
This bit is only valid while the ANNC bit 10 is 1
1 = A common operation mode was not found
0 = A-N is complete and a common operation mode has been found
PLR — Polarity Reversed (10BASE-T)
1 = 10BASE-T receive polarity is reversed
0 = 10BASE-T receive polarity is normal
12.3.4.3 Proprietary Control Register
MII Register Address 18 (%10010)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
W
0
FE
FLTD
MIILBD
0
1
JBDE
LNK
TSTD
POL
CORD
ALGD
ENC
BYP
SCR TRD TR
BYP ANALB TST
0
0
0
RESET: 0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-17. Proprietary Control Register
The miscellaneous (EMISC) register provides visibility of internal counters used by the EMAC.
Read: Anytime
Write: Anytime
MC9S12NE64 Data Sheet, Rev. 1.1
366
Freescale Semiconductor