MC9S12NE64_06 Datasheet, PDF(51/554 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC9S12NE64_06 Datasheet, PDF (51/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Signal Description

1.2.3.22 PG4 / KWG4 / MII_RXCLK â Port G I/O Pin 4

PG4 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

receive clock (MII_RXCLK) signal. It can be conï¬gured to generate an interrupt (KWG4) causing the

MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG4 pin is conï¬gured as

a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the EMAC block description chapter for information about pin conï¬gurations.

1.2.3.23 PG3 / KWG3 / MII_RXD3 â Port G I/O Pin 3

PG3 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

receive data (MII_RXD3) signal. It can be conï¬gured to generate an interrupt (KWG3) causing the MCU

to exit stop or wait mode. While in reset and immediately out of reset, the PG3 pin is conï¬gured as a

high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the EMAC block description chapter for information about pin conï¬gurations.

1.2.3.24 PG2 / KWG2 / MII_RXD2 â Port G I/O Pin 2

PG2 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

receive data (MII_RXD2) signal. It can be conï¬gured to generate an interrupt (KWG2) causing the MCU

to exit stop or wait mode. While in reset and immediately out of reset, the PG2 pin is conï¬gured as a

high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the EMAC block description chapter for information about pin conï¬gurations.

1.2.3.25 PG1 / KWG1 / MII_RXD1 â Port G I/O Pin 1

PG1 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

receive data (MII_RXD1) signal. It can be conï¬gured to generate an interrupt (KWG1) causing the MCU

to exit stop or wait mode. While in reset and immediately out of reset, the PG1 pin is conï¬gured as a

high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the EMAC block description chapter for information about pin conï¬gurations.

1.2.3.26 PG0 / KWG0 / MII_RXD0 â Port G I/O Pin 0

PG0 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

receive data (MII_RXD0) signal. It can be conï¬gured to generate an interrupt (KWG0) causing the MCU

to exit stop or wait mode. While in reset and immediately out of reset, the PG0 pin is conï¬gured as a

high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the EMAC block description chapter for information about pin conï¬gurations.

1.2.3.27 PH6 / KWH6 / MII_TXER â Port H I/O Pin 6

PH6 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

transmit error (MII_TXER) signal. It can be conï¬gured to generate an interrupt (KWH6) causing the MCU

to exit stop or wait mode. While in reset and immediately out of reset, the PH6 pin is conï¬gured as a

high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the EMAC block description chapter for information about pin conï¬gurations.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor

51

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