MC9S12NE64_06 Datasheet, PDF (69/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Definition
HCS12 core PPAGE register is used to map the logical middle page ranging from address 0x8000 to
0xBFFF to any physical 16 Kbyte page in the Flash memory. By placing 0x3E or 0x3F in the HCS12 Core
PPAGE register, the associated 16 Kbyte pages appear twice in the MCU memory map.
The FPROT register, described in Section 2.3.2.5, “Flash Protection Register (FPROT)”, can be set to
globally protect a Flash block. However, three separate memory regions, one growing upward from the
first address in the next-to-last page in the Flash block (called the lower region), one growing downward
from the last address in the last page in the Flash block (called the higher region), and the remaining
addresses in the Flash block, can be activated for protection. The Flash locations of these protectable
regions are shown in Table 2-2. The higher address region is mainly targeted to hold the boot loader code
because it covers the vector space. The lower address region can be used for EEPROM emulation in an
MCU without an EEPROM module because it can remain unprotected while the remaining addresses are
protected from program or erase.
Security information that allows the MCU to restrict access to the Flash module is stored in the Flash
configuration field, described in Table 2-1.
Table 2-1. Flash Configuration Field
Unpaged Flash
Address
0xFF00 - 0xFF07
0xFF08 - 0xFF0C
0xFF0D
0xFF0E
0xFF0F
Paged Flash Address
(PPAGE 0x3F)
0xBF00-0xBF07
Size
(bytes)
8
0xBF08-0xBF0C
5
0xBF0D
1
0xBF0E
1
0xBF0F
1
Description
Backdoor Comparison Key
Refer to Section Section 2.6.1,
“Unsecuring the MCU using
Backdoor Key Access”
Reserved
Flash Protection byte
Refer to Section 2.3.2.5, “Flash
Protection Register (FPROT)”
Flash Nonvolatile byte
Refer to Section 2.3.2.9, “Flash
Control Register (FCTL)”
Flash Security byte
Refer to Section 2.3.2.2, “Flash
Security Register (FSEC)”
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
69