MC9S12NE64_06 Datasheet, PDF (524/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.13.1.2 MII Transmit Signal Timing (TXD[3:0], TXEN, TXER, TXCLK)
Table A-15. MII Transmit Signal Timing
Num
M5
M6
M7
M8
Characteristic
TXCLK rise to TXD[3:0], TXEN, TXER invalid
TXCLK rise to TXD[3:0], TXEN, TXER valid
TXCLK pulse width high
TXCLK pulse width low
Min
0
—
35%
35%
Max
—
25
65%
65%
M7
Unit
ns
ns
TXCLK period
TXCLK period
TXCLK (input)
M5
M8
TXD[3:0] (outputs)
TXEN
TXER
M6
Figure A-2. MII Transmit Signal Timing Diagram
A.13.1.3 MII Asynchronous Inputs Signal Timing (CRS, COL)
Table A-16. MII Transmit Signal Timing
Num
M9
Characteristic
CRS, COL minimum pulse width
Min
Max
1.5
—
Unit
TXCLK period
MC9S12NE64 Data Sheet, Rev. 1.1
524
Freescale Semiconductor