MC9S12NE64_06 Datasheet, PDF (122/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9NE64V1)
Read:Anytime.
Write:Anytime.
This register selects whether a pull-down or a pull-up device is connected to the pin.
PPSG[7:0] — Pull Select Port G
1 = Rising edge on the associated port G pin sets the associated flag bit in the PIFG register. A
pull-down device is connected to the associated port G pin, if enabled by the associated bit in
register PERG and if the port is used as input.
0 = Falling edge on the associated port G pin sets the associated flag bit in the PIFG register. A
pull-up device is connected to the associated port G pin, if enabled by the associated bit in
register PERG and if the port is used as input.
3.3.2.3.7 Interrupt Enable Register (PIEG)
Module Base + $16
Read:
Write:
Reset:
Bit 7
PIEG7
0
6
PIEG6
0
5
PIEG5
0
4
PIEG4
0
3
PIEG3
0
2
PIEG2
0
1
PIEG1
0
Figure 3-21. Port G Interrupt Enable Register (PIEG)
Bit 0
PIEG0
0
Read:Anytime.
Write:Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port
G.
PIEG[7:0] — Interrupt Enable Port G
1 = Interrupt is enabled.
0 = Interrupt is disabled (interrupt flag masked).
3.3.2.3.8 Interrupt Flag Register (PIFG)
Module Base + $17
Read:
Write:
Reset:
Bit 7
PIFG7
0
6
PIFG6
0
5
PIFG5
0
4
PIFG4
0
3
PIFG3
0
2
PIFG2
0
Figure 3-22. Port G Interrupt Flag Register (PIFG)
1
PIFG1
0
Bit 0
PIFG0
0
Read:Anytime.
Write:Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSG register. To clear this flag, write a “1” to the corresponding bit in the PIFG register.
Writing a “0” has no effect.
MC9S12NE64 Data Sheet, Rev. 1.1
122
Freescale Semiconductor