MC9S12NE64_06 Datasheet, PDF (130/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.5.7 Interrupt Enable Register (PIEJ)
Module Base + $26
Bit 7
6
5
4
Read:
Write:
PIEJ7
PIEJ6
0
0
Reset:
0
0
—
—
3
PIEJ3
0
2
PIEJ2
0
1
PIEJ1
0
Bit 0
PIEJ0
0
= Reserved or unimplemented
Figure 3-37. Port J Interrupt Enable Register (PIEJ)
Read:Anytime.
Write:Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with
port J.
PIEJ[7:6][3:0]— Interrupt Enable Port J
1 = Interrupt is enabled.
0 = Interrupt is disabled (interrupt flag masked).
3.3.2.5.8 Interrupt Flag Register (PIFJ)
Module Base + $27
Bit 7
6
5
4
Read:
0
0
Write: ^PIFJ7
PIFJ6
Reset:
0
0
—
—
3
PIFJ3
0
2
PIFJ2
0
1
PIFJ1
0
Bit 0
PIFJ0
0
= Reserved or unimplemented
Figure 3-38. Port J Interrupt Flag Register (PIFJ)
Read:Anytime.
Write:Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write “1” to the corresponding bit in the PIFJ register.
Writing a “0” has no effect.
PIFJ[7:6][3:0] — Interrupt Flags Port J
1 = Active edge on the associated bit has occurred (an interrupt will occur if the associated enable
bit is set).
Writing a “1” clears the associated flag.
0 = No active edge pending.
Writing a “0” has no effect.
MC9S12NE64 Data Sheet, Rev. 1.1
130
Freescale Semiconductor