MC9S12NE64_06 Datasheet, PDF (121/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Descriptions
3.3.2.3.4 Reduced Drive Register (RDRG)
Module Base + $13
Read:
Write:
Reset:
Bit 7
RDRG7
0
6
RDRG6
0
5
RDRG5
0
4
RDRG4
0
3
RDRG3
0
2
RDRG2
0
1
RDRG1
0
Bit 0
RDRG0
0
Figure 3-18. Port G Reduced Drive Register (RDRG)
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port G output pin as either full or reduced. If the port is
used as input these bits are ignored.
RDRG[7:0] — Reduced Drive Port G
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
3.3.2.3.5 Pull Device Enable Register (PERG)
Module Base + $14
Read:
Write:
Reset:
Bit 7
PERG7
0
6
PERG6
0
5
PERG5
0
4
PERG4
0
3
PERG3
0
2
PERG2
0
1
PERG1
0
Bit 0
PERG0
0
Figure 3-19. Port G Pull Device Enable Register (PERG)
Read:Anytime.
Write:Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input.
These bits have no effect if the port is used as output. Out of reset no pull device is enabled.
PERG[7:0] — Pull Device Enable Port G
1 = Either a pull-up or pull-down device is enabled.
0 = Pull-up or pull-down device is disabled.
3.3.2.3.6 Polarity Select Register (PPSG)
Module Base + $15
Read:
Write:
Reset:
Bit 7
PPSG7
0
6
PPSG6
0
5
PPSG5
0
4
PPSG4
0
3
PPSG3
0
2
PPSG2
0
1
PPSG1
0
Bit 0
PPSG0
0
Figure 3-20. Port G Polarity Select Register (PPSG)
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
121