MC9S12NE64_06 Datasheet, PDF (342/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11 Ethernet Media Access Controller (EMACV1)
Table 11-11. Ethernet PAUSE Frame Structure
Preamble SFD
DA
SA
Type/Length
MAC Control
Opcode
MAC Control
Parameters
Reserved
FCS
7 bytes
1 byte
6 bytes =
(01-80-C2-00-00-01)
or
unique DA
6 bytes
2 bytes =
MAC Control
(88-08)
2 bytes =
(00-01)
2 bytes = 42 bytes = 4 bytes
(00-00 to FF-FF) all 0s
11.4.5.2 Hardware Generated PAUSE Control Frame Transmission
As long as there is no transmission in progress and EMAC is in full-duplex mode, a PAUSE command can
be launched by writing to the TCMD field. The EMAC builds a PAUSE frame according to Table 11-11
using the parameter value in the PTIME field and then transmits this frame. The DA field is set to
01-80-C2-00-00-01 (hex).
When the transmitted PAUSE frame is complete, the TXCIF bit is set. If not masked (TXCIE set to 1) the
EMAC generates the frame transmission complete interrupt.
NOTE
To transmit a MAC flow control pause frame using a unique DA, the user
must construct a valid pause frame in the transmit buffer, configure the
TXEFP register, and issue a START command. However, whenever issuing
pause frames in this manner, the command is suspended while the received
pause time counter value (PTIME) is nonzero and is sent after the time has
expired.
11.4.5.3 PAUSE Control Frame Reception
While RFCE bit is set, the receiver detects PAUSE frames in full-duplex mode. Upon PAUSE frame
detection, the RFCIF bit in the IEVENT register is asserted and the EMAC transmitter stops transmitting
data frames for a duration after the current transmission is complete. The duration is given by the PAUSE
time parameter in the received frame. If not masked (RFCIE is set), a receive flow control interrupt is
pending while this flag is set. Although the reception of a PAUSE frame stops transmission of frames
initiated with a START command, it does not prevent transmission of PAUSE control frames. PAUSE
frames may be accepted even if both receive buffers are full.
11.4.6 MII Management
MII management access to a PHY is via the MII_MDC and MII_MDIO signals. MII_MDC has a
maximum clock rate of 2.5 MHz. MII_MDIO is bidirectional and can be connected to 32 external devices
or the internal PHY. When using the internal PHY, the MII_MDC and MII_MDIO signals are not visible
to the user.
MC9S12NE64 Data Sheet, Rev. 1.1
342
Freescale Semiconductor