MC9S12NE64_06 Datasheet, PDF (119/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Descriptions
3.3.2.2.7 Wired-Or Mode Register (WOMS)
Module Base + $E
Read:
Write:
Reset:
Bit 7
WOMS7
0
6
WOMS6
0
5
WOMS5
0
4
WOMS4
0
3
WOMS3
0
2
WOMS2
0
1
WOMS1
0
Bit 0
WOMS0
0
Figure 3-14. Port S Wired-Or Mode Register (WOMS)
Read:Anytime.
Write:Anytime.
This register configures the output pins as wired-or. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a
multipoint connection of several serial modules. These bits have no influence on pins used as inputs.
WOMS[7:0] — Wired-Or Mode Port S
1 = Open-drain mode enabled for output buffers.
0 = Open-drain mode disabled for output buffers.
3.3.2.3 Port G Registers
3.3.2.3.1 I/O Register (PTG)
Module Base + $10
Read:
Write:
EMAC
KWU
Reset:
Bit 7
PTG7
—
—
6
5
4
3
2
1
Bit 0
PTG6
PTG5
PTG4
PTG3
PTG2
PTG1
PTG0
MII_RXER MII_RXDV MII_RXCLK MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
KWG
0
0
0
0
0
0
0
Figure 3-15. Port G I/O Register (PTG)
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read. The EMAC MII external interface takes precedence over
general-purpose I/O function if the EMAC module is enabled in external PHY mode. If the EMAC is
enabled PG[6:0] pins become inputs MII_RXER, MII_RXDV, MII_RXCLK, MII_RXD[3:0]. Please refer
to the EMAC block description chapter for details.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
119