MC9S12NE64_06 Datasheet, PDF (325/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Descriptions
Table 11-5. MII Management Frame Operation
BUSY
OP
1
xx
0
00
0
01
0
10
0
11
Operation
Ignore
Ignore
Write
Read
Ignore
BUSY — Operation in Progress
This read-only status bit indicates MII management activity. BUSY is asserted after a valid OP write
and is cleared when the MMCIF flag is set.
1 = MII is busy (operation in progress).
0 = MII is idle (ready for operation).
NOPRE — No Preamble
Any value written while BUSY is set is ignored. The IEEE 802.3 standard allows the preamble to be
dropped if the attached PHY does not require it. While this bit is set, a preamble is not prepended to
the MII management frame.
1 = No preamble is sent.
0 = 32-bit preamble is sent.
MDCSEL — Management Clock Rate Select
Any value programmed while BUSY bit is set is ignored. This field controls the frequency of the MII
management data clock (MDC) relative to the IP bus clock. MDC toggles only during a valid MII
management transaction. While MDC is not active, it remains low. Any nonzero value results in an
MDC frequency given by the following formula:
MDC frequency = Bus clock frequency / (2 * MDCSEL)
The MDCSEL field must be programmed with a value to provide an MDC frequency of less-than or
equal-to 2.5 MHz to be compliant with the IEEE MII specification. The MDCSEL must be set to a
nonzero value in order to source a read or write MII management frame.
Table 11-6. Programming Examples for MDCSEL
IP Bus Clock Frequency
20 MHz
25 MHz
33 MHz
40 MHz
50 MHz
MDCSEL
0x4
0x5
0x7
0x8
0xA
MDC Frequency
2.5 MHz
2.5 MHz
2.36 MHz
2.5 MHz
2.5 MHz
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
325