MC9S12NE64_06 Datasheet, PDF (188/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Timer Module (TIM16B4CV1)
6.3.2.1 Timer Input Capture/Output Compare Select (TIOS)
7
6
5
4
3
2
1
0
R
0
0
0
0
IOS7
IOS6
IOS5
IOS4
W
Reset
0
0
0
0
0
0
0
0
Figure 6-6. Timer Input Capture/Output Compare Select (TIOS)
Read: Anytime
Write: Anytime
Table 6-2. TIOS Field Descriptions
Field
7:4
IOS[7:4]
Description
Input Capture or Output Compare Channel Configuration
0 The corresponding channel acts as an input capture.
1 The corresponding channel acts as an output compare.
6.3.2.2 Timer Compare Force Register (CFORC)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W FOC7
FOC6
FOC5
FOC4
Reset
0
0
0
0
0
0
0
0
Figure 6-7. Timer Compare Force Register (CFORC)
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
Table 6-3. CFORC Field Descriptions
Field
Description
7:4
FOC[7:4]
Force Output Compare Action for Channel 7:4 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A successful channel 7 output compare overrides any channel 6:4 compares. If forced output compare on
any channel occurs at the same time as the successful output compare then forced output compare action
will take precedence and interrupt flag won’t get set.
MC9S12NE64 Data Sheet, Rev. 1.1
188
Freescale Semiconductor