MC9S12NE64_06 Datasheet, PDF (197/554 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map and Register Definition
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
NOTE
Read/Write access in byte mode for high byte should takes place before low
byte otherwise it will give a different result.
6.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
7
R
0
W
6
5
4
3
2
1
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 6-22. 16-Bit Pulse Accumulator Control Register (PACTL)
When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7.
Read: Any time
Write: Any time
Table 6-17. PACTL Field Descriptions
Field
6
PAEN
5
PAMOD
4
PEDGE
3:2
CLK[1:0]
Description
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table 6-18.
0 Event counter mode.
1 Gated time accumulation mode.
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See Table 6-18.
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
edge on IOC7 sets the PAIF flag.
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
on IOC7 sets the PAIF flag.
Clock Select Bits — Refer to Table 6-19.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
197