EP7211 Datasheet, PDF (99/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.4.2 MEMCFG2 Memory Configuration Register 2
ADDRESS: 0x8000.01C0
31
24
23
16
15
8
7
0
(Boot ROM)
(Local SRAM)
NCS5 configuration
NCS4 configuration
The memory configuration register 2 is a 32-bit read/write register which sets the configuration of
the two expansion and ROM selects NCS4–NCS5. Each select is configured with a 1-byte field
starting with expansion select 4.
Each of the six non-reserved byte fields for chip select configuration in the memory configuration
registers are identical and define the number of wait states, the bus width, enable EXPCLK output
during accesses and enable sequential mode access. This byte field is defined below. This
arrangement applies to NCS0–3, and NCS4–5 when the PC CARD enable bits in the SYSCON2
register are not set. The state of these bits is ignored for the Boot ROM and local SRAM fields in the
MEMCFG2 register.
7
6
5
2
1
0
CLKENB
SQAEN
Wait States Field
Bus width
Table 5-4.Values of the Bus Width Field defines the bus width field. Note that the effect of this
field is dependent on the two BOOTBIT bits that can be read in the SYSFLG register. All bits in the
memory configuration register are cleared by a system reset and the state of the BOOTBIT bits are
determined by Port E bits 0 and 1 on the EP7211 during power-on reset. The state of PE1 and PE0
determine whether the EP7211 is going to boot from either 32-bit wide, 16-bit wide or 8-bit wide
ROMs.
Table 5-4. Values of the Bus Width Field
Bus Width
Field
00
01
10
11
00
01
10
11
00
01
10
BOOTBIT1 BOOTBIT0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
Expansion Transfer
Mode
32-bit wide bus access
16-bit wide bus access
8-bit wide bus access
Reserved
8-bit wide bus access
Reserved
32-bit wide bus access
16-bit wide bus access
16-bit wide bus access
32-bit wide bus access
Reserved
Port E bits 1,0 during
NPOR reset
Low, Low
Low, Low
Low, Low
Low, Low
Low, High
Low, High
Low, High
Low, High
High, Low
High, Low
High, Low
DS352PP3
JUL 2001
99
Register Descriptions