EP7211 Datasheet, PDF (104/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.7 PMPCON Pump Control Register
ADDRESS: 0x8000.0400
11:8
Drive 1 pump ratio
7:4
Drive 0 from AC source ratio
3:0
Drive 0 from battery ratio
The Pulse Width Modulator (PWM) pump control register is a 16-bit read/write register which sets
and controls the variable mark space ratio drives for the two PWMs. All bits in this register are
cleared by a system reset. (The top four bits are unused. They should be written as zeroes, and will
read as undefined).
Bit
Description
0:3
Drive 0 from battery: This 4-bit field controls the ‘on’ time for the drive0 PWM pump while the system is
powered from batteries. Setting these bits to 0 disables this pump, setting these bits to 1 allows the pump
to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio etc. up to a 15:16 duty ratio. An 8:16 duty ratio results
in a square wave of 96 kHz when operating with an
18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz source.
4:7
Drive 0 from AC: This 4-bit field controls the ‘on’ time for the drive0 DC to DC pump while the system is
powered from a non-battery type power source. Setting these bits to 0 disables this pump, setting these
bits to 1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc. up to a 15:16 duty
ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating with an 18.432 MHz master
clock, or 101.6 kHz when operating from the 13 MHz source.
NOTE: The EP7211 monitors the power supply input pins (i.e., BATOK and NEXTPWR) to determine
which of the above fields to use.
8:11
Drive 1 pump ratio: This 4-bit field controls the ‘on’ time for the drive1 PWM pump. Setting these bits to 0
disables this pump, setting these bits to 1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty
ratio, etc. up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating
with an 18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz source.
The state of the output drive pins is latched during power on reset, this latched value is used to
determine the polarity of the drive output. The sense of the PWM control lines is summarized in
Table 5-9.
Table 5-9. Sense of PWM control lines
Initial State of Driven During
Power on Reset
Low
High
Sense of Driven
Active high
Active low
Polarity of Bias
Voltage
+ve
-ve
External input pins that would normally be connected to the output from comparators monitoring the
PWM output are also used to enable these clocks. These are the FB[0:1] pins. They are read upon
power-up. When FB[0] is high, the PWM is disabled. The same applies to FB[1].
NOTE: To maximize power savings, the drive ratio fields should be used to disable the PWMs, instead of the
FB pins. The clocks that source the PWMs are disable when the drive ratio fields are zeroed.
104
Register Descriptions
DS352PP3
JUL 2001