EP7211 Datasheet, PDF (40/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 3-4 summarizes the three external interrupt sources and the effect they have on interrupt pins.
Table 3-4. External Interrupt Source Latencies
Interrupt
Pin
NEXTFIQ
NEINT1–2
EINT3
MEDCHG
Input State
Not deglitched;
must be active for
20 µs to be
detected
Not deglitched
Not deglitched
Deglitched by
16 kHz clock; must
be active for at
least 80 µs to be
detected
Operating
State
Latency
Worst case
latency of 20
µs
Worst case
latency of 20
µs
Worst case
latency of 20
µs
Worst case
latency of 80
µs
Idle State
Latency
Worst case 20
µs: if only sin-
gle cycle
instructions,
less than
1 µs
As above
As above
Worst case 80
µs: if only sin-
gle cycle
instructions,
61 µs
Standby State Latency
Including PLL/osc. settling time,
approx. 0.25 s when FASTWAKE
= 0, or approx. 500 µs when
FASTWAKE = 1, or = Idle State if
in 13 MHz mode with CLENSL set
As above
As above
As above (note difference if in 13
MHz mode with CLKENSL set)
For the case of the keyboard interrupt, the following options are available and are selectable
according to bits 1 and 3 of the SYSCON2 register (refer to SYSCON2 register description for
details).
• If the KBWEN bit (SYSCON2 Bit 3) is set low, then a keypress will cause a transition from a
power saving state only if the keyboard interrupt is non-masked (i.e., the interrupt mask register
2 (INTMR2 bit 0) is high).
• When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the
interrupt mask register. This is called the “Keyboard Direct Wakeup’ mode. In this mode, the
interrupt request may not get serviced. If the interrupt is masked (i.e., the interrupt mask register
2 (INTMR2 bit 0) is low), the processor simply starts re-executing code from where it left off
before it entered the power saving state. If the interrupt is non-masked, then the processor will
service the interrupt.
• When the KBD6 bit (SYSCON2 Bit 1) is low, all 8 of Port A inputs are OR’ed together to
produce the internal wakeup signal and keyboard interrupt request. This is the default reset
state.
• When the KBD6 bit (SYSCON2 Bit 1) is high, only the lowest 6 bits of Port A are OR’ed
together to produce the internal wakeup signal and keyboard interrupt request. The two most
significant bits of Port A are available as GPIO when this bit is set high.
40
Functional Description
DS352PP3
JUL 2001