EP7211 Datasheet, PDF (101/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-6. Values of the Wait State Field at 36 MHz (cont.)
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
1
Wait States
Random
1
Wait States
Sequential
0
The previous table preserves compatibility with the previous devices, while allowing the previously
unused bit combinations to specify more variations of random and sequential wait states.
Bit
6
7
Description
SQAEN: Sequential access enable. Setting this bit will enable sequential accesses that are on a quad
word boundary to take advantage of faster access times from devices that support page mode. The
sequential access will be faulted after four words, (to allow video refresh cycles to occur) even if the
access is part of a longer sequential access. In addition, when this bit is not set, non-sequential accesses
will have a single idle cycle inserted at least every four cycles so that the chip select is de-asserted period-
ically between accesses for easier debug.
CLKENB: Expansion clock enable. Setting this bit enables the EXPCLK to be active during accesses to
the selected expansion device. This will provide a timing reference for devices that need to extend bus
cycles using the EXPRDY input. Back to back (but not necessarily page mode) accesses will result in a
continuous clock. This bit will only affect EXPCLK when the PLL is being used (i.e., in 73.728–18.432MHz
mode). When operating in 13 MHz mode, the EXPCLK pin is an input so cannot be affected by this regis-
ter bit. To save power internally, it should always be set to zero when operating in 13 MHz mode.
See the AC Electrical Specification section for more detail on bus timing.
The memory area decoded by CS6 is reserved for the on-chip SRAM, hence this does not require a
configuration field in MEMCFG2. It is automatically set up for 32-bit wide, no wait state accesses.
For the Boot ROM, it is automatically set up for 8-bit, no wait state accesses.
Chip selects NCS4 and NCS5 are used to select two CL-PS6700 PC CARD controller devices. These
have a multiplexed 16-bit wide address/data interface, and the configuration bytes in the MEMCFG2
register have no meaning when these interfaces are enabled.
5.4.3 DRFPR DRAM Refresh Period Register
ADDRESS: 0x8000.0200
7
RFSHEN
6:0
RFDIV
The DRAM refresh period register is an 8-bit read/write register which enables refreshes and selects
the refresh period used by the DRAM controller for its periodic CAS before RAS refresh. The value
DS352PP3
JUL 2001
101
Register Descriptions