EP7211 Datasheet, PDF (66/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
3.10 Internal UARTs (Two) and SIR Encoder
The EP7211 contains two built-in UARTs that offers similar functionality to National
Semiconductor’s 16C550A device. Both UARTs can support bit rates of up to 115.2 Kbps and
include two 16-byte FIFOs: one for receive and one for transmit.
One of the UARTs (UART1) supports the three modem control input signals CTS, DSR and DCD.
The additional RI input, and RTS and DTR output modem control lines are not explicitly supported
but can be implemented using GPIO ports in the EP7211. UART2 has only the RX and TX pins.
UART operation and line speeds are controlled by the UBLCR1 (UART bit rate and line control).
Three interrupts can be generated by UART1: RX, TX, and modem status interrupts. Only two can
be generated by UART2: RX and TX. The RX interrupt is asserted when the RX FIFO becomes half
full or if the FIFO is non-empty for longer than three character length times with no more characters
being received. The TX interrupt is asserted if the TX FIFO buffer reaches half empty. The modem
status interrupt for UART1 is generated if any of the modem status bits change state. Framing and
parity errors are detected as each byte is received and pushed onto the RX FIFO. An overrun error
generates an RX interrupt immediately. All error bits can be read from the 11-bit wide data register.
The FIFOs can also be programmed to be one byte depth only (i.e., like a conventional 16450 UART
with double buffering).
The EP7211 also contains an IrDA (Infrared Data Association) SIR protocol encoder as a post-
processing stage on the output of UART1. This encoder can be optionally switched in to the TX and
RX signals of UART1, so that these can be used to drive an infrared interface directly. If the SIR
protocol encoder is enabled, the UART TXD1 line is held in the passive state and transitions of the
RXD1 line will have no effect. The IrDA output pin is LEDDRV, and the input from the photodiode
is PHDIN. Modem status lines will cause an interrupt (which can be masked) irrespective of whether
the SIR interface is being used.
Both the UARTs operate in a similar manner to the industry standard 16C550A. When CTS is
deasserted on the UART, the UART does not stop shifting the data. It relies on software to take
appropriate action in response to the interrupt generated.
Baud rates supported for both the UARTs are dependent on frequency of operation. When operating
from the internal PLL, the interface supports various baud rates from 115.2 kbps downwards. The
master clock frequency is chosen so that most of the required data rates are obtainable exactly. When
operating with a 13.0 MHz external clock source, the baud rates generated will have a slight error,
which is less than or equal to 0.75%. The rates obtainable from the 13 MHz clock include 9.6 k, 19.2
k, 38 k, 58 k and 115.2 kbps. See Section 5.9.2 in the register programming section of this spec for
full details of the available bit rates in the 13 MHz mode.
3.11 Timer Counters
Two identical timer counters are integrated into the EP7211. These are referred to as TC1 and TC2.
Each timer counter has an associated 16-bit read/write data register and some control bits in the
system control register. Each counter is loaded with the value written to the data register
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Functional Description
DS352PP3
JUL 2001